C5ENPB0-DS Datasheet, PDF (33/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

Pin Descriptions Grouped by Function
33
Clock Signals Table 6 describes the C-5e NP clock signals.
Table 6 Clock and Reference Signals
SIGNAL NAME PIN #
TOTAL TYPE
I/O SIGNAL DESCRIPTION
SCLK*
SCLKX*
G15
1
F15
1
LVPECL I
LVPECL I
Core Clock Rate (Differential)
CCLK0
CCLK1
CCLK2
CCLK3
CCLK4
CCLK5
CCLK6
CCLK7
CPREF‡
TOTAL
G14
1
F14
1
E14
1
G13
1
F13
1
E13
1
F12
1
E12
1
G12
1
11
LVTTL I_PD 1_544MHZ_CLK (T1)†
LVTTL I_PD 2_048MHZ_CLK (E1)†
LVTTL I_PD 34_368MHZ_CLK (E3)†
LVTTL I_PD 44_736MHZ_CLK (T3)†
LVTTL I_PD 50MHZ_CLK (100Mbit Ethernet)†
LVTTL I_PD 106_25MHZ_CLK (Fibre Channel)†
LVTTL I_PD 125MHZ_CLK (Gigabit Ethernet)†
LVTTL I_PD 155_52MHZ_CLK (OC-3)†
LVPECL I_PD Reference
* _{SCLK and SCLKX must not be AC-coupled.}
† _{The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5e NP. It is also possible to use one}
or more CCLKn inputs for other frequencies. Contact your Freescale representative for more information.
‡ _{If any of the CPs are configured for LVPECL operation (OC3) using the pin mode registers, then CPREF must}
be wired to an external reference, as specified in Table 38 on page 77. If none of the CPs are configured for
LVPECL operation, then the CPREF pin can be left unconnected.
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08