C5ENPB0-DS Datasheet, PDF (109/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

Package Measurements 109
Package Measurements
Table 61 defines the C-5e NP package measurements, providing nominal, minimum, and
maximum sizes where appropriate.
Table 61 Package Measurements (Reference Figure 28, and Figure 29 for Symbols)
SYMBOL DEFINITION
NOM. (MM) MIN. (MM) MAX. (MM)
A
Overall
3.26
2.97
3.55
A₁
Ball height
0.70
0.6
0.8
A₂
Die height
0.86
0.82
0.9
A₃
Body thickness 1.7
1.55
1.85
A₄
Capacitor height
0.6
D
Body size
31.00
30.80
31.20
D₁
Ball footprint (X) 28.00
E
Body size
31.00
30.80
31.20
E₁
Ball footprint (Y) 28.00
e
Ball pitch
1.00
b
Ball diameter 0.70
Keep Out Zones
Figure 30 shows the C-5e NP keep out zones and Table 62 defines their measurements,
providing minimum and maximum sizes where appropriate.
Since 14 capacitors are present on all devices, caution must be taken not to short
capacitors or exposed metal capacitor pads on package top. This can be achieved by
noting the capacitors zones as detailed here.
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08