C5ENPB0-DS Datasheet, PDF (116/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

116 INDEX
Power Supply 59
PROM Interface 45
QMU External Mode Interface 58
QMU SRAM (Internal Mode) Interface 57
Serial Interface 44
Serial Port 45
Test 60
TLU SRAM Interface 56
SONET OC-12 Transceiver Interface Configuration 41
SONET OC-3 Transceiver Interface Configuration 41
Specifications
10/100 Ethernet Timing 86
AC Timing 83
BMU Timing 99
Clock Timing 84
CP Timing 85
DS1/DS3 Timing 85
Electrical 75
Executive Processor Timing 92
Fabric Processor Timing 97
Gigabit GMII Ethernet, TBI and MII Interface Timing
Specification 87
Low Speed Serial Interface Timing 95
MDIO Serial Interface Timing 94
Mechanical 107
OC-12 Timing 91
OC-3 Timing 89
PCI Timing 92
PROM Interface Timing 96
QMU Timing 102
TLU Timing 100
XP Timing 92
System Clock Timing Description 84
System Clock Timing Diagram 84
System Interfaces
Executive Processor 25
T
Table Lookup Unit 27
Test Signals 60
Test Signals, Miscellaneous, For JTAG, Scan, and Internal Test
Routines 60
Timing Outline
PROM Interface 48
C5ENPB0-DS REV 08
TLU Signal Groups 101
TLU SRAM Interface Signals 56
TLU Timing Description 100
TLU Timing Diagram 100
TLU Timing Specifications 100
Transceiver Interface Configuration
SONET OC-12 41
SONET OC-3 41
Transmit and Receive Pin Combinations for Gigabit Ethernet and
FibreChannel 37
U
Utopia2/Utopia3 ATM Mode, C-5e Network Processor to Fabric
Interface Pin Mapping 50
Utopia2/Utopia3 PHY Mode, C-5e Network Processor to Fabric
Interface Pin Mapping 51
X
XP Timing Specifications 92
FREESCALE SEMICONDUCTOR