C5ENPB0-DS Datasheet, PDF (47/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

Pin Descriptions Grouped by Function
47
The PROM interface operates in the following manner (Note that two accesses are
piplined together to execute one 32-bit fetch). The steps are shown in Figure 6.
1 The PROM_ADDR is loaded into the network processor internal shift register.
2 The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles.
3 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external
presentation register.
4 SPLD is deasserted for 22 SPCLK cycles. The PROM presents the first 16bit PROM_DATA.
At the same time, the next PROM_ADDR is shifted into the external shift register.
5 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external
presentation register and the first PROM_DATA into the external shift register.
6 SPLD is deasserted for 22 SPCLK cycles, shifting the first PROM_DATA into the network
processor internal shift register.
7 SPLD is asserted for one SPCLK cycle, loading the first PROM_DATA into the network
processor PROM_RETURN_DATA register and the second PROM_DATA into the
external shift register.
8 SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the
network processor internal shift register.
9 SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the
network processor PROM_RETURN_DATA register.
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08