C5ENPB0-DS Datasheet, PDF (85/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

AC Timing Specifications
85
† _{The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5e NP. It is also possible to use one}
or more CCLKn inputs for other frequencies; contact your Freescale representative for more information.
CP Timing Specifications
This section describes the timing for the following CP interfaces:
• DS1/DS3
• 10/100 Ethernet
• Gigabit Ethernet
• OC-3
• OC-12
DS1/DS3 Timing Specifications
The DS1/DS3 interface timing is shown in Figure 14 and described in Table 42.
Figure 14 DS1/DS3 Ethernet Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
CPn_0 (TCLK)
CPn_2/3 (Tx)
T_cdt
T_cdo
CPn_1 (RCLK)
CPn_4/5 (Rx)
Cycle 2
Cycle 3
T_cdr
T_cds T_cdh
Cycle 4
Cycle 5
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08