C5ENPB0-DS Datasheet, PDF (71/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

JTAG Support
71
JTAG Support
The C-5e NP contains Joint Test Action Group (JTAG) test logic compliant with the IEEE
1149.1 specification. All required public instructions are implemented, as well as some
optional instructions. This section contains information regarding the pinout, instructions,
identification codes, and boundary scan cell types.
Pinout The C-5e NP uses the standard JTAG pins including the optional test reset pin. Table 30
describes the pins, their functions, and termination circuits required to ensure predictable
NP behavior.
JTAG Data Registers The C-5e NP contains the standard internal registers as specified in IEEE 1149.1. These
registers are described in Table 33.
Table 33 JTAG Internal Register Descriptions
REGISTER NAME
Bypass
Boundary
Device Identification
REGISTER LENGTH
1
1549
32
DESCRIPTION
Standard JTAG bypass register
Boundary Scan Register
Standard JTAG IDCODE Register
Boundary Scan Cell Types
The C-5e NP boundary scan register contains only two cell types. All input cells are observe
only cells of type BC_4. All enable and output cells are standard cells of type BC_1. In IEEE
1149.1-1990 specification, the BC_4 cell is shown in Figure 7 and the BC_1 cell is shown in
Figure 8.
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08