C5ENPB0-DS Datasheet, PDF (105/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

AC Timing Specifications 105
Table 59 QMU External Mode Timing Description
SYMBOL PARAMETER
Tqec QMU External Cycle Time
Tqep QMU CLKA-CLKB delta
between rising edges
Tqes QMU Input Data Setup
Tqeh QMU Input Data Hold
Tqeo QMU Data Output
Tr, Tf QACLKI, QBCLKI Rise, Fall
MIN TYP MAX UNIT COMMENT
10.0
ns QACLKO/QBCLKO
derived from
QACLKI/QBCLKI
4.8
ns
0.6
ns
0.8
ns
-.85
1.3 ns Determines valid time
for data from each clock
rising edge
2.0 * ns
* _{Measured 0.8V to 2.0V.}
Table 60 Signal Groups in QMU External Mode Timing Diagrams
SIGNAL GROUP
Input Clocks (QnCLKI)
Output Clocks (QnCLKO)
Input Data (DQDATA)
Output Data (NQDATA)
INCLUDED SIGNALS
QACLKI, QBCLKI
QACLKO, QBCLKO
QD0-23, QARDY, QDPL, QDPH, QNQRDY, QDQPAR
QA0-16, QWEX, QD24-31
Although the C-5e NP provides an external mode, it does not support an external traffic
manager device.
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08