C5ENPB0-DS Datasheet, PDF (48/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

48
CHAPTER 2: SIGNAL DESCRIPTIONS
Figure 6 PROM Interface Timing Outline
XP PROM Interface outline
SPLD
`
`
`
`
`
SPDTO
A1
A2
A3
A4
A5
SPDTI
D1
D2
D3
XP PROM Interface detail
SPCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7
SPLD
SPDTO
1
SPDTI
A1
x
AAAAAAAAAAA
21 20 19 18 17 16 15 14 13 12 11
AA
10 9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
CE
The PROM_ADDR is loaded into the
C-5's internal shift register.
The PROM_ADDR is shifted into
the external shift register.
2
(SPCLK Rising Edge used for shifting)
A2
35
The PROM_ADDR is loaded into the
external presentation register.
The PROM_DATA is
presenting.
A3
A4
4
The PROM_DATA is loaded into the
external shift register.
D1
D2
x
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
DD
43
D
2
D
1
D
0
x
x
x
x
x
x
68
The PROM_DATA is shifted into the C-5's
Internal shift register.
7 9 The PROM_DATA is loaded into the C-5's
internal PROM_RETURN_DATA register.
C5ENPB0-DS REV 08
General System Interface Signal
Table 18 provides the signal for the Executive Processor reset power status and I/O clock.
The C-5e NP can be powered up with the XP either running or with the XP in reset mode
similar to the CPs. When the XP remains in reset mode, an external host can be used to
control the initialization of the C-5e NP.
FREESCALE SEMICONDUCTOR