C5ENPB0-DS Datasheet, PDF (60/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

60
CHAPTER 2: SIGNAL DESCRIPTIONS
Test Signals Test signals are described in Table 30.
Table 30 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines
SIGNAL NAME
JTCK
PIN #
C15
TOTAL TYPE I/O
1
LVTTL I_PD
JTMS
A14
1
LVTTL I_PD
JTRSTX†
JTDI†
JTDO
JHIGHZ
JCLKBYP
JSE
JS00-JS05
TOTAL PINS
A12
B14
A13
B13
C14
D15
D14, A16, D13, C12, A15, B12
1
LVTTL I_PD
1
LVTTL I_PD
1
LVTTL O
1
LVTTL I_PD
1
LVTTL I_PD
1
LVTTL I_PD
6
LVTTL O
14
SIGNAL DESCRIPTION
JTAG Test Clock. External pull-up
resistor required if not open.¹
JTAG Test Mode Select. External pull-up
resistor required if not open. High
selects modes as defined in the IEEE
1149.1 JTAG specification.¹
JTAG Test Reset. External pull-down
resistor required if not open (low
active).¹
JTAG Test Data In. External pull-up
resistor required if not open.¹
JTAG Test Data Out. No external pull
required.¹
Internal pull-down. High turns off all
output drivers.²
Internal pull-down selects 1X clock
mode when open (recommended).
High selects 2X clock mode. ²
Internal pull-down. High enables scan
test.²
No internal pull. Scan out pins.²
1 _{JTAG test signal. If JTAG is not used, this pin may be left open because it is internally pulled to turn JTAG off. However, if this pin is connected to an}
external circuit, an external pull-up or pull-down resistor is required as noted in the “Signal Descriptions” column. 4.7 kohm is sufficient for external
pull-up or pull-down on JTAG signals.
2 _{Manufacturing test signal not supported for customer use. This pin should be left open.}
During JTAG, SCLK and SCLKX must remain as differential inputs.
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR