C5ENPB0-DS Datasheet, PDF (55/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

Pin Descriptions Grouped by Function
55
Table 25 BMU SDRAM Interface Signals (continued)
SIGNAL NAME
MRASX
PIN #
C19
MWEX
B19
MCSX
A19
MDQM
G18
MDQML
F18
MDCLK
B18
TOTAL PINS
TOTAL TYPE
1
LVTTL
1
LVTTL
1
LVTTL
1
LVTTL
1
LVTTL
1
LVTTL
160
I/O SIGNAL DESCRIPTION
O_PD Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered. MCSX
is considered part of the command code.
O_PD Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered. MCSX
is considered part of the command code.
O_PD Chip Select: MCSX enables (registered LOW) and
disables (registered HIGH) the command decoder.
All commands are masked when MCSX is
registered HIGH. MCSX provides the external bank
selection on systems with multiple banks. MCSX is
considered part of the command code.
O_PD Input/Output Mask: MDQM is an input mask
O_PD
signal for write accesses and an output enable
signal for read accesses. Input data is masked
when MDQM is sampled HIGH during a WRITE
cycle. The output buffers are placed in a high Z
state (two-clock latency) when MDQM is sampled
HIGH during the READ cycle.
NOTE: MDQML is an identical copy of MDQM
used to drive the loading on SDRAM
configurations with 2 DQM pins.
I_PD Clock: MDCLK is driven by the system clock. All
SDRAM input signals are sampled on the positive
edge of the MDCLK. MDCLK also increments the
internal burst counter and controls the output
registers.
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08