C5ENPB0-DS Datasheet, PDF (96/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

96
CHAPTER 3: ELECTRICAL SPECIFICATIONS
SPCK
SPDI
SPLD
SPDO
Cycle 1
PROM Interface Timing Specifications
The PROM interface timing is shown in Figure 22 and described in Table 51.
Figure 22 PROM Interface Timing Diagram
Cycle 2
Cycle 3
Cycle 4
Cycle 5
T_spc
T_splo
T_spis T_spih
T_spdo
Table 51 PROM Interface Timing Description
SYMBOL PARAMETER
MIN
TYP
Tspc
SPCK Cycle Time 40.0
Tspis SPDI Setup
10.0
Tspih SPDI Hold
0.0
Tsplo SPLD Output Tsc
Tspdo SPDO Output Tsc
MAX
UNIT
ns
ns
ns
Tsc + 3.0 ns
Tsc + 3.0 ns
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR