C5ENPB0-DS Datasheet, PDF (54/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

54
CHAPTER 2: SIGNAL DESCRIPTIONS
BMU SDRAM Interface
Signals
The BMU and SDRAM interface signals are described in Table 25.
The BMU is designed to support SDRAM devices with 12 address lines. All 139 data lines
and all 12 address lines must be connected to the SDRAM in order for the BMU to be able
to read and write external SDRAM properly.
Table 25 BMU SDRAM Interface Signals
SIGNAL NAME
PIN #
TOTAL TYPE
MD0 - MD129
U23, U22, U21, T29, T28, T27, T26, 130
T25, T24, T23, T22, T21, R29, R28,
R27, R26, R25, R24, R23, R22, R21,
P29, P28, P26, P25, P24, P22, P21,
N29, N27, N26, N25, N23, N22, N21,
M29, M28, M27, M26, M25, M24,
M23, M22, M21, L29, L28, L27, L26,
L25, L24, L23, L22, L21, K29, K28,
K26, K25, K24, K22, K21, J29, J27,
J26, J25, J23, J22, J21, H29, H28,
H27, H26, H25, H24, H23, H22, H21,
G29, G28, G27, G26, G25, G24, G23,
G22, G21, F29, F28, F26, F25, F24,
F22, F21, E29, E27, E26, E25, E23,
E22, E21, D29, D28, D27, D26, D25,
D24, D23, D22, D21, C29, C28, C26,
C25, C24, C22, C21, B29, B27, B26,
B25, B23, B22, B21, A29, A28, A27,
A26, A25, A24, A23, A22
LVTTL
MDECC0 - MDECC8 E19, F19, G19, A20, C20, D20, F20, 9
G20, A21
LVTTL
MA0 - MA11
B16, C16, D16, E16, F16, G16, A17, 12
B17, D17, E17, F17, G17
LVTTL
MBA0 - MBA1
E18, C18
MCASX
D19
2
LVTTL
1
LVTTL
I/O SIGNAL DESCRIPTION
I_PD/O Data Lines
I_PD/O Stored as data, ECC bits
O_PD Address Outputs: A0-A11 are sampled during the
ACTIVE command and READ/WRITE to select one
location out of the memory array in the respective
bank. The address inputs also provide the
op-code during a LOAD MODE REGISTER
command
O_PD Bank Address Outputs: BA0 and BA1 define which
bank the ACTIVE, READ, WRITE or PRECHARGE
command is being applied
O_PD Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered.
NOTE: MCSX is considered part of the command
code.
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR