C5ENPB0-DS Datasheet, PDF (45/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

Pin Descriptions Grouped by Function
45
Which of the two data rates used is selected by the state of the PROM interface’s SPLD
signal that is asserted while the PROM interface is idle. When SPLD is asserted HI the low
speed serial bus protocol is selected and when SPLD is asserted LOW the MDIO protocol is
selected.
The bus only supports a single master hierarchy that can operate as either a receiver or a
transmitter.
Both SIDA and SICL are bidirectional lines that are connected, through a pull-up resistor, to
a positive supply voltage. When the bus is free, both lines are HIGH. The output stages of
the devices connected to the bus must have either an open-drain or open-collector in
order to perform the wired-AND function required for its arbitration mechanism.
Table 16 Serial Interface Signals
SIGNAL NAME
SICL
SIDA
TOTAL PINS
PIN #
Y5
Y6
TOTAL TYPE
1
LVTTL
1
LVTTL
2
I/O SIGNAL DESCRIPTION
I_PD/O Serial Clock line
I_PD/O Serial Data line
FREESCALE SEMICONDUCTOR
PROM Interface Signals
The PROM interface is a low speed I/O port that allows the C-5e NP to communicate
through external logic to PROM. The PROM clock is ¹/₂ to ¹/₁₆ the core clock rate. The
maximum PROM size addressable is 4MBytes, and must use a “by 16” part. The PROM
signals are listed in Table 17.
Table 17 PROM Interface Signals
SIGNAL
NAME
SPDO
SPDI
PIN #
Y1
Y2
TOTAL TYPE I/O SIGNAL DESCRIPTION
1
LVTTL O Serial Data Out
1
LVTTL I_PD Serial Data In
C5ENPB0-DS REV 08