C5ENPB0-DS Datasheet, PDF (72/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

72
CHAPTER 2: SIGNAL DESCRIPTIONS
Figure 7 Observe-Only Cell
From System Pin
G1
0
1
To next cell
To System Logic
1D
C1
Figure 8 Cell Design That Can Be Used for Both Input and Output Pins
Node
To/From
System Pin
Shift DR
G1
To next cell
G1
0
1
0
1D
1D
1
C1
C1
From last cell Clock DR
Update DR
From/To
System
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR