C5ENPB0-DS Datasheet, PDF (93/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

AC Timing Specifications
93
Table 48 PCI Timing Description
SYMBOL PARAMETER
MIN TYP
Tpc
PCI Cycle Time*
15.0
Tpas PAD/P_ctl† Setup
3.0
Tpah PAD/P_ctl Hold
0.0
Tpao PAD/P_ctl Output
2.0
Tpaz PAD/P_ctl Clk to Tri‡
2.0
Tpav PAD/P_ctl Clk to Driven‡ 2.0
Tpgs PGNTX Setup
5.1
Tpgh PGNTX Hold
0.0
Tpis
PIDSEL Setup
3.0
Tpih
PIDSEL Hold
0.0
PRSTX**
PINTA**
MAX UNIT
ns
ns
ns
6.0 ns
6.0 ns
6.0 ns
ns
ns
ns
ns
ns
ns
* _{66MHz PCI}
† _{P_ctl includes all PCI control parameters including: PPAR, PFRAMEX, PTRDYX, PIRDYX,}
PSTOPX, PDEVSELX, PPERRX, PSERRX
‡ _{Not fully tested, values based on design/characterization.}
** _Asynchronous
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08