C5ENPB0-DS Datasheet, PDF (25/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

Executive Processor
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Executive Processor
The Executive Processor (XP) serves as a centralized computing resource for the C-5e NP
and manages the system interfaces.
The XP performs conventional supervisory tasks in the C-5e NP, including:
• Reset and initialization of the C-5e NP
• Program loading and control of CPs
• Centralized exception handling
• Management of a host interface through the PCI
• Management of system interfaces (PCI, Serial Bus, PROM)
System Interfaces
The system interfaces to the XP are:
• PCI — Provides an industry standard 32bit 33/66MHz PCI channel used for chip-level
shared resources. The PCI has both initiator and target capabilities. The PCI interface is
typically connected to a host processor.
• Serial Bus Interface — Provides a general purpose bi-directional, two-wire serial bus
and I/O port that allows the C-5e NP to control external logic with either of two
standard protocols:
– The MDIO (high-speed) protocol: uses a 16bit data format with 10bits of
addressing and supports transfers up to 25MHz.
– The low-speed protocol: uses an 8bit data format followed by an acknowledge bit
and supports transfers up to 400kbps.
Software is used to select which protocol to use, by setting the appropriate bits in the
Serial Bus Configuration Register. When a serial bus transfer is active, an external pin is
driven by the C-5e NP to indicate which protocol is being used (SPLD=0 indicates
MDIO protocol; SPLD=1 indicates low-speed protocol).
Both SIDA and SICL are bi-directional lines that are connected, via an external pull-up
resistor, to a positive supply voltage. When the bus is free, both lines are HIGH because
of the pull-up resistor. The output stages of the devices connected to the bus must
have either an open-drain or open-collector in order to perform the wired-AND
function required for its arbitration mechanism.
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08