C5ENPB0-DS Datasheet, PDF (52/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 22 PRIZMA Mode, C-5e Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS
C-5e NETWORK
PROCESSOR
I/O
FRXCTL1
Output
FRXCTL2
Input
FRXCTL3
Input
FRXCTL4
Input
FRXCTL5
Input
FRXCTL6
Input
UTOPIA
TxClav
TxSOP
n/a
n/a
n/a
TxPrty
NOTE
No connection
Optional
TRANSMIT SIGNALS
C-5e NETWORK
PROCESSOR
I/O
FTXCTL1
Output
FTXCTL2
Output
FTXCTL3
Input
FTXCTL4
Input
FTXCTL5
Input
FTXCTL6
Output
* _{Both TxEnb and RxEnb are Active Low.}
Table 23 Power X(CSIX-L0) Mode, C-5e Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS
C-5e NETWORK
PROCESSOR
FRXCTL0
FRXCTL1
FRXCTL2
FRXCTL3
FRXCTL4
FRXCTL5
FRXCTL6
I/O
Input
Input
Input
Input
Input
Input
Input
POWER X
RxCtrl[0]
RxCtrl[1]
RxCtrl[2]
RxPrty[3]
RxPrty[2]
RxPrty[1]
RxPrty[0]
NOTE
TRANSMIT SIGNALS
C-5e NETWORK
PROCESSOR
I/O
FTXCTL0
Output
FTXCTL1
Output
FTXCTL2
Output
FTXCTL3
Output
FTXCTL4
Output
FTXCTL5
Output
FTXCTL6
Output
For the CSIX-L1 Mode, VDDF= 2.5V.
UTOPIA
RxClav
RxSOP
n/a
n/a
n/a
RxPrty
NOTE
No Connection
Optional
POWER X
TxCtrl[0]
TxCtrl[1]
TxCtrl[2]
TxPrty[3]
TxPrty[2]
TxPrty[1]
TxPrty[0]
NOTE
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR