C5ENPB0-DS Datasheet, PDF (57/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

Pin Descriptions Grouped by Function
57
QMU SRAM (Internal The QMU signals are described in Table 27.
Mode) Interface Signals
Table 27 QMU SRAM (Internal Mode) Interface Signals
SIGNAL NAME
QA0 - QA16
QD0 - QD31
QDQPAR
QARDY
QNQRDY
QWEX
QBCLKO
QBCLKI
QACLKO
QACLKI
PIN #
C8, B8, A8, F9, E9, D9, C9, B9, A9, F10, D10, C10,
A10, G11, F11, E11, D11
G1, F1, E1, D1, C1, B1, G2, F2, D2, C2, A2, G3, E3,
D3, B3, A3, G4, F4, E4, D4, C4, B4, A4, G5, F5, E5,
D5, C5, B5, A5, F6, D6
C11
E8
D8
C6
A6
E7
D7
B7
QDPL
A7
QDPH
F8
TOTAL PINS
TOTAL TYPE
17 LVTTL
32 LVTTL
1
LVTTL
1
LVTTL
1
LVTTL
1
LVTTL
1
LVTTL
1
LVTTL
1
LVTTL
1
LVTTL
1
LVTTL
1
LVTTL
59
I/O SIGNAL DESCRIPTION
O Address [16:0]
I_PD/O Data
I_PD nc
I_PD nc
I_PD nc
O Write Enable
O nc
I_PD nc
O nc
I_PD Input Clock (drives QMU and
external SRAM)
I_PD/O Data Parity Low
I_PD/O Data Parity High
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08