MC68HC08AS20 Datasheet, PDF (94/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. (For maximum immunity guidelines, refer to
document numbers AN1050/D and AN1263/D on electromagnetic
compatibility available from your Freescale sales office.) The VCO
frequency is bound to a range from roughly one-half to twice the
center-of-range frequency, f_VRS. Modulating the voltage on the CGMXFC
pin changes the frequency within this range. By design, f_VRS is equal to
the nominal center-of-range frequency, f_NOM, 4.9152 MHz times a linear
factor (L) or f_NOM.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a crystal frequency, f_RCLK, and is fed to the PLL
through a buffer. The buffer output is the final reference clock,
CGMRDV, running at a frequency equal to f_RCLK.
The VCO’s output clock, CGMVCLK, running at a frequency f_VCLK is fed
back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor, N (see 8.4.2.4 Programming the
PLL). The divider’s output is the VCO feedback clock, CGMVDV,
running at a frequency equal to f_VCLK/N. See 21.9 CGM Operating
Conditions for more information.
The phase detector then compares the VCO feedback clock (CGMVDV)
with the final reference clock (CGMRDV). A correction pulse is
generated based on the phase difference between the two signals. The
loop filter then slightly alters the dc voltage on the external capacitor
connected to CGMXFC, based on the width and direction of the
correction pulse. The filter can make fast or slow corrections, depending
on its mode, described in 8.4.2.2 Acquisition and Tracking Modes.
The value of the external capacitor and the reference frequency
determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, f_RD. The circuit determines the mode of the PLL and the lock
condition based on this comparison.
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor