MC68HC08AS20 Datasheet, PDF (346/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

20.7 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the
BDLC and consists of five user registers.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 20-14. BDLC Block Diagram
20.7.1 BDLC Analog and Roundtrip Delay
This register programs the BDLC to compensate for various delays of
different external transceivers. The default delay value is 16 µs. Timing
adjustments from 9 µs to 24 µs in steps of 1 µs are available. The BARD
register can be written only once after each reset, after which they
become read-only bits. The register may be read at any time.
Address:
Read:
Write:
Reset:
$003B
Bit 7
ATE
1
6
5
0
RXPOL
1
0
= Unimplemented
4
3
2
1
Bit 0
0
BO3
BO2
BO1
BO0
0
0
1
1
1
Figure 20-15. BDLC Analog and Roundtrip Delay Register (BARD)
Advance Information
346
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor