MC68HC08AS20 Datasheet, PDF (341/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

20.6.1 Protocol Architecture
The protocol handler contains the state machine, Rx shadow register, Tx
shadow register, Rx shift register, Tx shift register, and loopback
multiplexer as shown in Figure 20-13.
BDRxD
TO PHYSICAL INTERFACE
BDTxD
DLOOP FROM BCR2
LOOPBACK CONTROL
LOOPBACK
MULTIPLEXER
STATE MACHINE
Rx SHIFT REGISTER
Rx SHADOW REGISTER
8
Tx SHIFT REGISTER
Tx SHADOW REGISTER
8
TO CPU INTERFACE AND Rx/Tx BUFFERS
Figure 20-13. BDLC Protocol Handler Outline
20.6.2 Rx and Tx Shift Registers
The Rx shift register gathers received serial data bits from the J1850 bus
and makes them available in parallel form to the Rx shadow register. The
Tx shift register takes data, in parallel form, from the Tx shadow register
and presents it serially to the state machine so that it can be transmitted
onto the J1850 bus.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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