MC68HC08AS20 Datasheet, PDF (325/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

communication path through the analog transceiver to be tested without
interfering with network activity. Using the BDLC analog loopback mode
in conjunction with the analog transceiver’s loopback mode ensures that,
once the off-chip analog transceiver has exited loopback mode, the
BCLD will not begin communicating before a known condition exists on
the J1850 bus.
20.5 BDLC MUX Interface
The MUX interface is responsible for bit encoding/decoding and digital
noise filtering between the protocol handler and the physical interface.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 20-3. BDLC Block Diagram
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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