MC68HC08AS20 Datasheet, PDF (368/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

21.5 5.0 Volt DC Electrical Characteristics
Characteristic
Output High Voltage
(I_Load = –2.0 mA) All Ports, RESET
Output Low Voltage
(I_Load = 1.6 mA) All Ports, RESET
Input High Voltage
All Ports, IRQs, RESET, OSC1
Input Low Voltage
All Ports, IRQs, RESET, OSC1
V_DD + V_DDA/V_DDAREF Supply Current
Run (see Note 3)
Wait (see Note 4)
Stop (see Note 5)
25 °C
–40 °C to +105 °C
25 °C with LVI Enabled
–40 °C to +105 °C with LVI Enabled
I/O Ports Hi-Z Leakage Current
Input Current
Capacitance
Ports (As Input or Output)
Low-Voltage Reset Inhibit
Low-Voltage Reset Recover
Low-Voltage Reset Inhibit/Recover Hysteresis
POR ReArm Voltage (see Note 6)
POR Reset Voltage (see Note 7)
POR Rise Time Ramp Rate (see Note 8)
High COP Disable Voltage (see Note 9)
Symbol
V_OH
V_OL
V_IH
V_IL
Min
Typ
V_DD –0.8
—
—
—
Max
—
0.4
0.7 x V_DD
—
V_DD
V_SS
—
0.3 x V_DD
Unit
V
V
V
V
I_DD
I_L
I_IN
C_OUT
C_IN
V_LVII
V_LVIR
H_LVI
V_POR
V_PORRST
R_POR
V_HI
—
—
30
mA
—
—
15
mA
—
—
5
µA
—
—
50
µA
—
—
400
µA
—
—
500
µA
—
—
±1
µA
—
—
±1
µA
—
—
—
12
—
8
pF
3.8
4.0
4.2
V
4.0
4.2
4.4
V
100
200
500
mV
0
—
200
mV
0
—
800
mV
0.02
—
—
V/ms
V_DD
V_DD + 2
V
NOTES:
1. V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = –40 °C to +105 °C, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (Operating) I_DD measured using external square wave clock source (f_OP = 8.4 MHz). All inputs 0.2 V from rail.
No dc loads. Less than 100 pF on all outputs. C_L = 20 pF on OSC2. All ports configured as inputs. OSC2 capaci-
tance linearly affects run I_DD. Measured with all modules enabled.
4. Wait I_DD measured using external square wave clock source (f_OP = 8.4 MHz). All inputs 0.2 Vdc from rail. No dc
loads. Less than 100 pF on all outputs, C_L = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance
linearly affects wait I_DD. Measured with all modules enabled.
5. Stop I_DD measured with OSC1 = V_SS.
6. Maximum is highest voltage that POR is guaranteed.
7. Maximum is highest voltage that POR is possible.
8. If minimum V_DD is not reached before the internal POR reset is released, RST must be driven low externally until
minimum V_DD is reached.
9. See 13.9 COP Module During Break Interrupts.
Advance Information
368
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor