MC68HC08AS20 Datasheet, PDF (171/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Table 14-1. IRQ I/O Register Summary
Addr.
Register Name
Bit 7 6
5
4
3
Read: 0
0
0
0
IRQF
$001A IRQ Status/Control Register (ISCR)
Write:
Reset: 0
0
0
0
0
= Unimplemented
2
1 Bit 0
0
IMASK MODE
ACK
0
0
0
The external interrupt pin is falling-edge triggered and is software-
configurable to be both falling-edge and low-level triggered. The MODE
bit in the ISCR controls the triggering sensitivity of the IRQ pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains
set until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt latch remains set until both of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the ISCR masks all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the corresponding IMASK bit is clear.
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
(See Figure 14-2.)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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