MC68HC08AS20 Datasheet, PDF (362/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

halted is after at least one byte plus two extra logic 1s have been
transmitted. The receiver will pick this up as an error and relay it in the
state vector register as an invalid symbol error.
NOTE:
The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
on the J1850 bus from corrupting a message.
20.8 Low-Power Modes
The following information concerns wait mode and stop mode.
20.8.1 Wait Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a WAIT instruction and the WCM bit in
BDLC control register 1 (BCR1) is previously clear. In BDLC wait mode,
the BDLC cannot drive any data.
A subsequent successfully received message, including one that is in
progress at the time that this mode is entered, will cause the BDLC to
wake up and generate a CPU interrupt request if the interrupt enable (IE)
bit in the BDLC control register 1 (BCR1) is previously set (see 20.7.2
BDLC Control Register 1 for a better understanding of IE). This results
in less of a power saving, but the BDLC is guaranteed to receive
correctly the message which woke it up, since the BDLC internal
operating clocks are kept running.
NOTE: Ensuring that all transmissions are complete or aborted before putting
the BDLC into wait mode is important.
20.8.2 Stop Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a STOP instruction or if the CPU executes
a WAIT instruction and the WCM bit in the BDLC control register 1
(BCR1) is previously set. This is the lowest power mode that the BDLC
can enter.
Advance Information
362
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor