MC68HC08AS20 Datasheet, PDF (167/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

13.4.7 COPL (COP Long Timeout)
The COPL bit selects the state of the COP long timeout bit (COPL) in the
MOR register ($001F). Timeout periods can be 8,176 or 262,128
CGMXCLK cycles. (See 5.4 Mask Option Register.)
13.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
Read:
Write:
Reset:
5
4
3
2
Low Byte of Reset Vector
Clear COP Counter
Unaffected by Reset
1
Bit 0
Figure 13-2. COP Control Register (COPCTL)
13.6 Interrupts
The COP does not generate CPU interrupt requests.
13.7 Monitor Mode
The COP is disabled in monitor mode when V_DD + V_HI (see 21.5 5.0 Volt
DC Electrical Characteristics) is present on the IRQ pin or on the RST
pin.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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