MC68HC08AS20 Datasheet, PDF (320/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

20.4 Functional Description
Figure 20-1 shows the organization of the BDLC module. The CPU
interface contains the software addressable registers and provides the
link between the CPU and the buffers. The buffers provide storage for
data received and data to be transmitted onto the J1850 bus. The
protocol handler is responsible for the encoding and decoding of data
bits and special message symbols during transmission and reception.
The MUX interface provides the link between the BDLC digital section
and the analog physical interface. The wave shaping, driving, and
digitizing of data is performed by the physical interface.
Use of the BDLC module in message networking fully implements the
SAE Standard J1850 Class B Data Communication Network Interface
specification.
NOTE:
It is recommended that the reader be familiar with the SAE J1850
document and ISO Serial Communication document prior to proceeding
with this section of the MC68HC08AS20 specification.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 20-1. BDLC Block Diagram
.
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor