MC68HC08AS20 Datasheet, PDF (150/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

11.4.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether module status
bits can be cleared during the break state. The BCFE bit in the SIM break
flag control register (SBFCR) enables software to clear status bits during
the break state. (See 9.8.3 SIM Break Flag Control Register and the
Break Interrupts subsection for each module.)
11.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC–$FFFD
($FEFC–$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
11.4.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
11.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V_DD + V_HI is present
on the RST pin. For V_HI, see 21.5 5.0 Volt DC Electrical
Characteristics.
11.5 Break Module Registers
Three registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor