MC68HC08AS20 Datasheet, PDF (144/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

LVISTOP — LVI Disable in Stop Mode Bit
This read/write bit turns off the low-voltage inhibit module (LVI) in stop
mode when clear.
1 = LVI not disabled during stop mode
0 = LVI disabled during stop mode
NOTE:
To meet the stop mode I_DD specification, LVISTOP must be at logic 0.
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the
V_LVII voltage. (See Table 10-2.) Reset clears the LVIOUT bit.
Table 10-2. LVIOUT Bit Indication
V_DD
V_DD > V_LVIR
V_DD < V_LVII
V_LVII < V_DD < V_LVIR
LVIOUT
0
1
Previous Value
10.6 LVI Interrupts
The LVI module does not generate interrupt requests.
10.7 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power standby
modes.
10.7.1 Wait Mode
With the LVIPWRD bit in the MOR register programmed to logic 0, the
LVI module is active after a WAIT instruction.
With the LVIRSTD bit in the MOR register programmed to logic 0, the LVI
module can generate a reset and bring the MCU out of wait mode.
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor