MC68HC08AS20 Datasheet, PDF (103/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

8.6 CGM Registers
These registers control and monitor operation of the CGM:
• PLL control register (PCTL) (See 8.6.1 PLL Control Register.)
• PLL bandwidth control register (PBWC) (See 8.6.2 PLL
Bandwidth Control Register.)
• PLL programming register (PPG) (See 8.6.3 PLL Programming
Register.)
Table 8-2 is a summary of the CGM registers.
Addr.
$001C
Table 8-2. CGM I/O Register Summary
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PLLF
1
1
1
1
PLL Control Register
(PCTL)
Write:
PLLIE
PLLON BCS
Reset: 0
0
1
0
1
1
1
1
Read:
LOCK
0
0
0
0
$001D
PLL Bandwidth Control
Register (PBWC)
Write:
AUTO
ACQ
XLD
Reset: 0
0
0
0
0
0
0
0
$001E
Read:
PLL Programming Register
(PPG)
Write:
Reset:
MUL7
0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
VRS6 VRS5
1
1
VRS4
0
= Unimplemented
NOTES:
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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