MC68HC08AS20 Datasheet, PDF (156/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

12.4.1 Entering Monitor Mode
Table 12-1 shows the pin conditions for entering monitor mode.
Table 12-1. Mode Selection
Mode
CGMOUT
Bus
Frequency
V_DD +
V_HI(1)
1 0 1 1 Monitor
C-----G----M-----X-----C----L---K--- _or C-----G----M-----V-----C----L---K---
2
2
C-----G----M------O----U----T---
2
V_DD +
V_HI(1)
1 0 1 0 Monitor
CGMXCLK
C-----G----M------O----U----T---
2
1. For V_HI see 21.5 5.0 Volt DC Electrical Characteristics and 21.2 Maximum Ratings
Enter monitor mode by either
• Executing a software interrupt instruction (SWI) or
• Applying a logic 0 and then a logic 1 to the RST pin.
The MCU sends a break signal (10 consecutive logic 0s) to the host
computer, indicating that it is ready to receive a command. The break
signal also provides a timing reference to allow the host to determine the
necessary baud rate.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt.
The alternate vectors are in the $FE page instead of the $FF page and
allow code execution from the internal monitor firmware instead of user
code. The COP module is disabled in monitor mode as long as
V_DD + V_HI (see 21.5 5.0 Volt DC Electrical Characteristics) is applied
to either the IRQ pin or the V_DD pin. (See Section 9. System
Integration Module (SIM) for more information on modes of operation.)
NOTE:
Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The CGMOUT frequency is
equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor