MC68HC08AS20 Datasheet, PDF (359/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

rapidly enter an interrupt service routine. This eliminates the need for the
user to maintain a duplicate state machine in software.
Address: $003E
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
I3
I2
I1
I0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 20-19. BDLC State Vector Register (BSVR)
I0, I1, I2, and I3 — Interrupt Source Bits
These bits indicate the source of the interrupt request that currently is
pending. The encoding of these bits are listed in Table 20-6.
Table 20-6. BDLC Interrupt Sources
BSVR I3 I2 I1 I0
Interrupt Source
Priority
$00 0 0 0 0
No Interrupts Pending
0 (Lowest)
$04 0 0 0 1
Received EOF
1
$08 0 0 1 0
Received IFR Byte (RXIFR)
2
$0C 0 0 1 1 BDLC Rx Data Register Full (RDRF)
3
$10 0 1 0 0 BDLC Tx Data Register Empty (TDRE)
4
$14 0 1 0 1
Loss of Arbitration
5
$18 0 1 1 0 Cyclical Redundancy Check (CRC) Error
6
$1C 0 1 1 1
Symbol Invalid or Out of Range
7
$20 1 0 0 0
Wakeup
8 (Highest)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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