MC68HC08AS20 Datasheet, PDF (108/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

8.6.3 PLL Programming Register
The PLL programming register contains the programming information for
the modulo feedback divider and the programming information for the
hardware configuration of the VCO.
Address:
Read:
Write:
Reset:
$001E
Bit 7
MUL7
0
6
MUL6
1
5
MUL5
1
4
MUL4
0
3
VRS7
0
2
VRS6
1
1
VRS5
1
Figure 8-5. PLL Programming Register (PPG)
Bit 0
VRS4
0
MUL[7:4] — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See 8.4.2 Phase-Locked Loop
Circuit (PLL).) A value of $0 in the multiplier select bits configures the
modulo feedback divider the same as a value of $1. Reset initializes
these bits to $6 to give a default multiply value of 6.
Table 8-3. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
0000
0001
0010
0011
VCO Frequency Multiplier (N)
1
1
2
3
1101
13
1110
14
1111
15
Advance Information
108
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor