MC68HC08AS20 Datasheet, PDF (314/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

19.8.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time
an ADC conversion completes.
Address: $0039
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Indeterminate after Reset
= Unimplemented
Figure 19-3. ADC Data Register (ADR)
19.8.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address: $003A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
ADIV2 ADIV1 ADIV0 ADICLK
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 19-4. ADC Input Clock Register (ADICLK)
ADIV2:ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 19-2
shows the available clock configurations. The ADC clock should be
set to approximately 1 MHz.
Advance Information
314
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor