MC68HC08AS20 Datasheet, PDF (283/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

BUS
CLOCK
MOSI
SCK
CPHA = 1
SCK
CPHA = 0
SCK CYCLE
NUMBER
WRITE
TO SPDR
INITIATION DELAY
MSB
BIT 6
BIT 5
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
BUS
CLOCK
WRITE
TO SPDR
BUS
CLOCK
EARLIEST LATEST
WRITE
TO SPDR
SCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
LATEST
EARLIEST
SCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
LATEST
Figure 18-6. Transmission Start Delay (Master)
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
283