MC68HC08AS20 Datasheet, PDF (348/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Table 20-3. BDLC Transceiver Delay
BARD Offset Bits BO[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Corresponding Expected
Transceiver’s Delays (µs)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
20.7.2 BDLC Control Register 1
This register is used to configure and control the BDLC.
Address: $003C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
IMSG CLKS
R1
R0
IE
WCM
Write:
R
R
Reset: 1
1
1
0
0
0
0
0
R = Reserved
Figure 20-16. BDLC Control Register 1 (BCR1)
Advance Information
348
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor