MC68HC08AS20 Datasheet, PDF (142/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

10.4 Functional Description
Figure 10-1 shows the structure of the LVI module. The LVI module
contains a bandgap reference circuit and comparator. The LVI power
disable bit, LVIPWRD, disables the LVI from monitoring V_DD voltage.
The LVI reset disable bit, LVIRSTD, disables the LVI module from
generating a reset when V_DD falls below a voltage, V_LVII. LVIPWRD and
LVIRSTD are in the MOR register ($001F) (see Section 5. Mask
Options). Once an LVI reset occurs, the MCU remains in reset until V_DD
rises above a voltage, V_LVIR. The output of the comparator controls the
state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
V_DD
LVISTOP
STOP INSTRUCTION
LOW V_DD
DETECTOR
FROM MOR
LVIRSTD
LVIPWRD
FROM MOR
LVI RESET
LVIOUT
Figure 10-1. LVI Module Block Diagram
Table 10-1. LVI I/O Register Summary
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT 0
0
0
0
0
LVISTOP LVILCK
$FE0F LVI Status Register (LVISR) Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor