MC68HC08AS20 Datasheet, PDF (22/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Figure
Title
Page
18-8
18-9
18-10
18-11
18-12
18-13
18-14
Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . 286
SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . 289
SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . . 290
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . 298
SPI Status and Control Register (SPSCR). . . . . . . . . . . . . 301
SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . 304
19-1
19-2
19-3
19-4
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
ADC Status and Control Register (ADSCR). . . . . . . . . . . . 311
ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . 314
ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . 314
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
20-20
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
BDLC Operating Modes State Diagram . . . . . . . . . . . . . . . 322
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
BDLC Rx Digital Filter Block Diagram . . . . . . . . . . . . . . . . 326
J1850 Bus Message Format (VPW). . . . . . . . . . . . . . . . . . 328
J1850 VPW Symbols with Nominal Symbol Times . . . . . . 332
J1850 VPW Received Passive Symbol Times . . . . . . . . . . 335
J1850 VPW Received Passive EOF
and IFS Symbol Times . . . . . . . . . . . . . . . . . . . . . . . . . 336
J1850 VPW Received Active Symbol Times . . . . . . . . . . . 337
J1850 VPW Received BREAK Symbol Times . . . . . . . . . . 338
J1850 VPW Bitwise Arbitrations. . . . . . . . . . . . . . . . . . . . . 339
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
BDLC Protocol Handler Outline . . . . . . . . . . . . . . . . . . . . . 341
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
BDLC Analog and Roundtrip Delay Register (BARD) . . . . 346
BDLC Control Register 1 (BCR1). . . . . . . . . . . . . . . . . . . .348
BDLC Control Register 2 (BCR2). . . . . . . . . . . . . . . . . . . .351
Types of In-Frame Response (IFR) . . . . . . . . . . . . . . . . . . 355
BDLC State Vector Register (BSVR) . . . . . . . . . . . . . . . . . 359
BDLC Data Register (BDR) . . . . . . . . . . . . . . . . . . . . . . . . 361
21-1
21-2
21-3
SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
BDLC Variable Pulse Width Modulation (VPW)
Symbol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Advance Information
22
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor