MC68HC08AS20 Datasheet, PDF (143/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

10.4.1 Polled LVI Operation
In applications that can operate at V_DD levels below the V_LVII level,
software can monitor V_DD by polling the LVIOUT bit. In the MOR register,
the LVIPWRD bit must be at logic 0 to enable the LVI module, and the
LVIRSTD bit must be at logic 1 to disable LVI resets.
10.4.2 Forced Reset Operation
In applications that require V_DD to remain above the V_LVII level, enabling
LVI resets allows the LVI module to reset the MCU when V_DD falls to the
V_LVII level. In the MOR register, the LVIPWRD and LVIRSTD bits must
be at logic 0 to enable the LVI module and to enable LVI resets.
10.5 LVI Status Register
The LVI status register flags V_DD voltages below the V_LVII level.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
LVISTOP LVILCK
Write:
Reset: 0
0
0
0
0
0
0
0
= Reserved
Figure 10-2. LVI Status Register (LVISR)
LVILCK — LVI Lock Bit
This read/write bit inhibits writing to the LVI status and control register.
When LVILCK is set, writing to the LVI status and control register has
no effect. The LVILCK bit can be cleared only by reset.
1 = LVISCR write-protected
0 = LVISCR not write-protected
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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