MC68HC08AS20 Datasheet, PDF (120/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Addr.
$FE00
Table 9-1. SIM I/O Register Summary
Register Name
Bit 7
6
5
4
3
Read:
SIM Break Status Register
(SBSR)
Write:
R
R
R
R
R
Reset:
$FE01
Read: POR PIN COP ILOP ILAD
SIM Reset Status Register
(SRSR)
Write:
Reset: 1
X
0
0
0
Read:
$FE03
SIM Break Flag Control Register
(SBFCR)
Write:
BCFE
R
R
R
R
Reset: 0
2
1
Bit 0
R
SBSW
R
0
0
LVI
0
0
X
0
R
R
R
R = Reserved
= Unimplemented X = Indeterminate
Table 9-2 shows the internal signal names used in this section.
Table 9-2. Signal Name Conventions
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
IAB
IDB
PORRST
IRST
R/W
Description
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
Advance Information
120
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor