MC68HC08AS20 Datasheet, PDF (345/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

In any case, if the bus fault is temporary, as soon as the fault is
cleared, the BDLC will resume normal operation. If the bus fault is
permanent, it may result in permanent loss of communication on the
J1850 bus. (See 20.7.4 BDLC State Vector Register.)
BREAK — Break
If a BREAK symbol is received while the BDLC is transmitting or
receiving, an invalid symbol (in BSVR) interrupt will be generated.
Reading the BSVR (see 20.7.4 BDLC State Vector Register) will
clear this interrupt condition. The BDLC will wait for the bus to idle,
then wait for a start-of-frame (SOF) symbol.
The BDLC cannot transmit a BREAK symbol. It only can receive a
BREAK symbol from the J1850 bus.
20.6.5.5 Summary
Table 20-2. BDLC J1850 Bus Error Summary
Error Condition
BDLC Function
Transmission Error
For invalid bits or framing symbols on non-byte boundaries, invalid
symbol interrupt will be generated. BDLC stops transmission.
Cyclical Redundancy Check (CRC) Error CRC error interrupt will be generated. The BDLC will wait for EOF.
Invalid Symbol: BDLC transmits, but
Receives Invalid Bits (Noise)
The BDLC will abort transmission immediately. Invalid symbol
interrupt will be generated.
Framing Error
Invalid symbol interrupt will be generated. The BDLC will wait for end
of frame (EOF).
Bus Short to V_DD
The BDLC will not transmit until the bus is idle. Invalid symbol
interrupt will be generated. EOF interrupt also must be seen before
another transmission attempt. Depending on length of the short,
LOA flag also may be set.
Bus Short to GND
Thermal overload will shut down physical interface. Fault condition is
seen as invalid symbol flag. EOF interrupt must also be seen
before another transmission attempt.
BDLC Receives BREAK Symbol
Invalid symbol interrupt will be generated. The BDLC will wait for the
next valid SOF.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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