MC68HC08AS20 Datasheet, PDF (371/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

21.8 5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency (see Note 3)
Master
Slave
f_BUS(M)
f_BUS(S)
f_BUS/128 dc f_BUS/2 f_BUS
MHz
Cycle Time
1
Master
Slave
t_cyc(M)
2
t_cyc(S)
1
128
t_cyc
—
2 Enable Lead Time
t_LEAD
15
—
ns
3 Enable Lag Time
t_LAG
15
—
ns
Clock (SCK) High Time
4
Master
Slave
t_W(SCKH)M
t_W(SCKH)S
100
50
—
ns
—
Clock (SCK) Low Time
5
Master
Slave
t_W(SCKL)M
t_W(SCKL)S
100
50
—
ns
—
Data Setup Time, Inputs
6
Master
Slave
t_SU(M)
45
t_SU(S)
5
—
ns
—
Data Hold Time, Inputs
7
Master
Slave
t_H(M)
0
t_H(S)
15
—
ns
—
Access Time, Slave (see Note 4)
8
CPHA = 0
CPHA = 1
t_A(CP0)
0
t_A(CP1)
0
40
ns
20
ns
9
Slave Disable Time, Hold Time to High-Impedance
State (see Note 5)
t_DIS
—
25
ns
Data Valid Time after Enable Edge (see Note 6)
10 Master
Slave
t_V(M)
—
t_V(S)
—
10
ns
40
ns
Data Hold Time, Outputs, after Enable Edge
11 Master
Slave
t_HO(M)
0
t_HO(S)
5
—
ns
—
ns
NOTES:
1. All timing is shown with respect to 30% V_DD and 70% V_DD, unless otherwise noted; assumes 100 pF load on all SPI
pins.
2. Item numbers refer to dimensions in Figure 21-1 and Figure 21-2.
3. f_BUS = the currently active bus frequency for the microcontroller.
4. Time to data active from high-impedance state
5. Hold time to high-impedance state
6. With 100 pF on all SPI pins
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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