MC68HC08AS20 Datasheet, PDF (377/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

21.15 BDLC Receiver VPW Symbol Timings
Characteristic
Number Symbol
Min
Typ
Max
Unit
Passive Logic 0
10
t_TRVP1
34
64
96
µs
Passive Logic 1
11
t_TRVP2
96
128
163
µs
Active Logic 0
12
t_TRVA1
96
128
163
µs
Active Logic 1
13
t_TRVA2
34
64
96
µs
Start of Frame (SOF)
14
t_TRVA3
163
200
239
µs
End of Data (EOD)
15
t_TRVP3
163
200
239
µs
End of Frame (EOF)
16
t_TRV4
239
280
320
µs
Break
18
t_TRV6
240
—
—
µs
NOTES:
1. f_BDLC = 1.048576 or 1.0 MHz, V_DD = 5.0 V ± 10%, V_SS = 0 V
2. The receiver symbol timing boundaries are subject to an uncertainty of 1 t_BDLC µs due to sampling considerations.
3. See Figure 21-3.
14
10
12
SOF
13
11
0
0
15
1
1
0
EOD
16
EOF
18
BRK
Figure 21-3. BDLC Variable Pulse Width Modulation (VPW) Symbol Timing
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
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