MC68HC08AS20 Datasheet, PDF (128/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

9.6 Program Exception Control
Normal, sequential program execution can be changed in three different
ways:
• Interrupts
– Maskable hardware CPU interrupts
– Nonmaskable software interrupt instruction (SWI)
• Reset
• Break interrupts
9.6.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 9-7 shows interrupt entry timing.
Figure 9-9 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced or the I bit is cleared.
(See Figure 9-8.)
MODULE
INTERRUPT
IAB
IDB
R/W
LAST
ADDRESS
SP
SP – 1
SP – 2
SP – 3
SP – 4
VECTOR VECTOR
ADDR. HIGH ADDR. LOW
NEW PC
NEW PC
+1
END OF PC – 1
PC – 1
LAST INSTR. LOW BYTE HIGH BYTE
X
A
CCR
VECTOR
HIGH
VECTOR
LOW
OPCODE
Figure 9-7. Hardware Interrupt Entry Timing
Advance Information
128
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor