MC68HC08AS20 Datasheet, PDF (116/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Additionally, a certain number of clock cycles, n_TRK, is required to
ascertain that the PLL is within the lock mode entry tolerance, ∆_LOCK.
Therefore, the acquisition time, t_ACQ, is an integer multiple of n_ACQ/f_RDV,
and the acquisition to lock time, t_AL, is an integer multiple of n_TRK/f_RDV.
Refer to 8.4.2 Phase-Locked Loop Circuit (PLL) for the value of f_RDV.
Also, since the average frequency over the entire measurement period
must be within the specified tolerance, the total time usually is longer
than t_Lock as calculated above.
In manual mode, it is usually necessary to wait considerably longer than
t_Lock before selecting the PLL clock (see 8.4.3 Base Clock Selector
Circuit), because the factors described in 8.10.2 Parametric
Influences on Reaction Time can slow the lock time considerably.
Advance Information
116
MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor