MC68HC08AS20 Datasheet, PDF(115/386 Page) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

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MC68HC08AS20 Datasheet, PDF (115/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

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8.10.4 Reaction Time Calculation

The actual acquisition and lock times can be calculated using the

equations in this subsection. These equations yield nominal values

under the following conditions:

â¢ Correct selection of filter capacitor, CF (See 8.10.3 Choosing a

Filter Capacitor.)

â¢ Room temperature operation

â¢ Negligible external leakage on CGMXFC

â¢ Negligible noise

The K factor in the equations is derived from internal PLL parameters.

KACQ is the K factor when the PLL is configured in acquisition mode, and

KTRK is the K factor when the PLL is configured in tracking mode. (See

8.4.2.2 Acquisition and Tracking Modes.)

tACQ

=

ï£«

ï£

V--f--R-D-D-D--V-A-ï£¸ï£¶

ï£«

ï£

-K----A8--C---Q-ï£¸ï£¶

tAL

=

ï£«

ï£

V--f--R-D-D-D--V-A-ï£¸ï£¶

ï£«

ï£

-K----4T--R---K-ï£¸ï£¶

tLOCK = tACQ + tAL

NOTE: There is an inverse proportionality between the lock time and the

reference frequency.

In automatic bandwidth control mode, the acquisition and lock times are

quantized into units based on the reference frequency. (See 8.4.2.3

Manual and Automatic PLL Bandwidth Modes.) A certain number of

clock cycles, nACQ, is required to ascertain that the PLL is within the

tracking mode entry tolerance, âTRK, before exiting acquisition mode.

MC68HC08AS20 â Rev. 4.1

Freescale Semiconductor

Advance Information

115

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