MC68HC08AS20 Datasheet, PDF (93/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

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Table 8-1. CGM I/O Register Summary
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PLLF
1
1
1
1
PLL Control Register
(PCTL)
Write:
PLLIE
PLLON BCS
Reset: 0
0
1
0
1
1
1
1
Read:
LOCK
0
0
0
0
PLL Bandwidth Control
Register (PBWC)
Write:
AUTO
ACQ
XLD
Reset: 0
0
0
0
0
0
0
0
Read:
PLL Programming Register
(PPG)
Write:
Reset:
MUL7
0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
VRS6 VRS5
1
1
VRS4
0
= Unimplemented
8.4.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually. Refer to 21.9 CGM Operating
Conditions for operating frequencies while reading this section.
8.4.2.1 Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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