MC68HC08AS20 Datasheet, PDF (307/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

INTERNAL
DATA BUS
READ DDRB/DDRB
WRITE DDRB/DDRD
RESET
WRITE PTB/PTD
READ PTB/PTD
DDRBx/DDRDx
PTBx/PTDx
ADC DATA REGISTER
DISABLE
PTBx/PTDx
ADC CHANNEL x
DISABLE
CONVERSION
INTERRUPT ^COMPLETE
LOGIC
AIEN
COCO
CGMXCLK
BUS CLOCK
ADC
ADC VOLTAGE IN
ADCVIN
CHANNEL
SELECT
ADCH[4:0]
ADC CLOCK
CLOCK
GENERATOR
ADIV[2:0] ADICLK
Figure 19-1. ADC Block Diagram
19.4.1 ADC Port I/O Pins
PTD6/ATD14/TCLK–PTD0/ATD8 and PTB7/ATD7–PTB0/ATD0 are
general-purpose I/O pins that are shared with the ADC channels.
The channel select bits (ADC status control register, $0038), define
which ADC channel/port pin will be used as the input signal. The ADC
overrides the port I/O logic by forcing that pin as input to the ADC. The
remaining ADC channels/port pins are controlled by the port I/O logic
and can be used as general-purpose I/O. Writes to the port register or
DDR will not have any affect on the port pin that is selected by the ADC.
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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