MC68HC08AS20 Datasheet, PDF (342/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

20.6.3 Rx and Tx Shadow Registers
Immediately after the Rx shift register has completed shifting in a byte of
data, this data is transferred to the Rx shadow register and RDRF or
RXIFR is set (see 20.7.4 BDLC State Vector Register). An interrupt is
generated if the interrupt enable bit (IE) in BCR1 is set. After the transfer
takes place, this new data byte in the Rx shadow register is available to
the CPU interface, and the Rx shift register is ready to shift in the next
byte of data. Data in the Rx shadow register must be retrieved by the
CPU before it is overwritten by new data from the Rx shift register.
Once the Tx shift register has completed its shifting operation for the
current byte, the data byte in the Tx shadow register is loaded into the
Tx shift register. After this transfer takes place, the Tx shadow register is
ready to accept new data from the CPU when the TDRE flag in the BSVR
is set.
20.6.4 Digital Loopback Multiplexer
The digital loopback multiplexer connects RxD to either BDTxD or
BDRxD, depending on the state of the DLOOP bit in the BCR2 (See
20.7.3 BDLC Control Register 2).
20.6.5 State Machine
All functions associated with performing the protocol are executed or
controlled by the state machine. The state machine is responsible for
framing, collision detection, arbitration, CRC generation/checking, and
error detection. The following sections describe the BDLC’s actions in a
variety of situations.
20.6.5.1 4X Mode
The BDLC can exist on the same J1850 bus as modules which use a
special 4X (41.6 kbps) mode of J1850 variable pulse width modulation
(VPW) operation. The BDLC cannot transmit in 4X mode, but it can
receive messages in 4X mode, if the RX4XE bit is set in BCR2. If the
Advance Information
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MC68HC08AS20 —Rev. 4.1
Freescale Semiconductor