MC68HC08AS20 Datasheet, PDF (57/386 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

ROMSEC — ROM Security Bit
ROMSEC enables the ROM security feature. Setting the ROMSEC bit
prevents reading of the ROM contents. Access to the ROM is denied
to unauthorized users of customer specified software.
1 = ROM security enabled
0 = ROM security disabled
LVIPWRD— LVI Power Disable Bit
LVIPWRD disables the LVI module. (See Section 10. Low-Voltage
Inhibit (LVI).)
1 = LVI module power disabled
0 = LVI module power enabled
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. (See
Section 10. Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. (See
16.6.2 Stop Mode.)
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE: If using an external crystal oscillator, do not set the SSREC bit.
COPL— COP Long Timeout Bit
COPL selects the long COP timeout period. (See Section 13.
Computer Operating Properly (COP).)
1 = COP timeout period is 262,128 CGMXCLK cycles
0 = COP timeout period is 8,176 CGMXCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
MC68HC08AS20 — Rev. 4.1
Freescale Semiconductor
Advance Information
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